1. Technical Field
The present invention relates to a chucking device and chucking method.
2. Related Art
In recent years, the importance of a power semiconductor device such as an insulated gate bipolar transistor (IGBT) or insulated gate type field effect transistor (MOSFET) as an environment-adaptive electronic device is increasing. A chucking device that holds a semiconductor substrate by vacuum chucking has been proposed in order to convey a semiconductor substrate along a manufacturing line, or fix the semiconductor substrate to a support stand, in the manufacturing step of the semiconductor device.
FIG. 20 is an illustration showing a heretofore known chucking device. The chucking device shown in FIG. 20 includes a base portion 101 in which ring-like or radial groove portions 102 are provided. Ventilation holes (a vacuum system) 103 and 104 linked to the groove portions 102 are vacuum drawn, thereby vacuum adsorbing a semiconductor substrate 1 onto the base portion 101 (for example, refer to U.S. Pat. No. 3,627,338 (FIG. 1), U.S. Pat. No. 3,747,282 (FIG. 1), and Japanese Patent No. 2,821,678).
Also, as another device, there is proposed a chucking method of a type (pin chuck type) whereby pin-like protruding portions that hold a semiconductor substrate are provided on the surface of a base portion, and the semiconductor substrate is held on the protruding portions. FIG. 21 is an illustration showing a heretofore known pin chuck type chucking device. Also, FIG. 22 is a plan view showing the chucking device of FIG. 21. The chucking device shown in FIGS. 21 and 22 includes a base portion 111 on which are provided a plurality of pin-like protruding portions 112 that are in contact with the central portion of the semiconductor substrate 1, a cylindrical peripheral portion 113 that is in contact with the outer peripheral portion of the semiconductor substrate 1, and a ventilation hole (a vacuum system) 114 that vacuum draws a space surrounded by the semiconductor substrate 1, base portion 111, and peripheral portion 113. The space surrounded by the semiconductor substrate 1, base portion 111, and peripheral portion 113 is vacuum drawn (e.g., a vacuum is generated therein) via the ventilation hole 114, bringing the semiconductor substrate 1 into contact with, and holding it on, the protruding portions 112 and peripheral portion 113 (for example, refer to JP-B-60-15147 (FIG. 2)).
However, with the pin chuck type chucking device, a portion of the semiconductor substrate 1 not in contact with the protruding portions 112 and peripheral portion 113 sags partially due to suction force when vacuum drawn. As a chucking device that eliminates this kind of problem, there is proposed a device such that, on a vacuum chucking fixed stand including a central portion having a plurality of protruding portions and an outer peripheral portion having a groove portion, the array pitch of the protruding portions is 2 mm or less, and the central portion and outer peripheral portion are each configured in such a way as to be evacuable (for example, refer to Japanese Patent No. 2,574,818).
In Japanese Patent No. 2,574,818, by simulating one portion of a semiconductor substrate supported between one protruding portion and an adjacent protruding portion of the pin-like protruding portions disposed in a lattice form with a model of a support beam with both ends free supported by the protruding portions, and calculating the concentrated load exerted on the protruding portions, the interval between the adjacent protruding portions (the array pitch) is calculated to be 2 mm or less. At this time, the thickness of the semiconductor substrate is 0.4 mm, and the tolerance range of the sagging of the semiconductor substrate between the protruding portions is −0.5 μm or more, +0.5 μm or less.
Also, with the pin chuck type chucking device, a problem occurs in that, due to the sagging of the semiconductor substrate between the protruding portions, the position of the point of contact of the semiconductor substrate surface with each protruding portion deviates more (hereafter referred to as wafer distortion) in comparison with a case of placing the semiconductor substrate on the protruding portions without vacuum drawing.
As a device that reduces the wafer distortion, there is proposed a device that includes a plurality of protruding portions for supporting a semiconductor substrate, and chucks and holds the semiconductor substrate supported on the protruding portions, wherein the optimal setting values of the array pitch of the protruding portions and the chucking force of the semiconductor substrate are set based on the thickness of the semiconductor substrate, the lattice density of the semiconductor substrate, the static friction coefficient of the semiconductor substrate, and the maximum acceleration of a stage on which the chucking device is placed (for example, refer to Japanese Patent No. 4,298,078).
With the technology shown in Japanese Patent No. 4,298,078, it is proposed that when holding a semiconductor substrate with a diameter of 200 mm (eight inches) using a pin chuck type chucking device having protruding portions arrayed in a lattice form, with the interval between adjacent protruding portions at 2 mm, the relationship between a chucking force P (N/m2) holding the semiconductor substrate and an interval (array pitch) L (m) between adjacent protruding portions satisfies Equation 1 and Equation 2 below when adopting a semiconductor substrate flatness tolerance value of 80 nm and a wafer distortion tolerance value of 5 nm for a 0.25 μm rule semiconductor process with a longitudinal elastic modulus of 1.69×1011 (N/m), and a semiconductor substrate thickness of 725 μm.P≦0.0033/L3  (1)L≦0.0125  (2)
Also, as another pin chuck type holding device, there is proposed a device including a plurality of protruding portions having a substrate placement surface on which a substrate is placed, a suction hole opening on the substrate placement surface formed in at least one of the plural protruding portions, and a base portion on which are provided the plurality of protruding portions, wherein the substrate placement surfaces of the plurality of protruding portions are disposed in the same horizontal plane (for example, refer to JP-A-2007-322806).
Also, as another pin chuck type chucking device, the following kind of device is proposed. A cooling mechanism is provided inside a plate main body of a cooling plate device acting as a chucking plate device, cooling a substrate placed on a placement surface of the plate main body. Plural support protrusions and plural auxiliary protrusions are formed on the placement surface of the plate main body, and the substrate is supported by first and second apex portion end surfaces of each of the support protrusions and auxiliary protrusions. A vacuum suction hole for vacuum sucking the substrate is formed in each support protrusion. Of each support protrusion, the first apex portion end surface in contact with the substrate has the kind of smoothness that adheres closely to the substrate when vacuum drawing the substrate to the vacuum suction hole (for example, refer to JP-A-2004-303961).
However, as a result of dedicated research by the inventor, the following has become clear. The thickness of a semiconductor substrate after the semiconductor device is completed in, for example, an IGBT is finished to in the region of 180 to 300 μm in a 1,800V breakdown voltage class, in the region of 120 to 200 μm in a 1,200V breakdown voltage class, and in the region of 60 to 90 μm in a 600V breakdown voltage class.
Furthermore, by adopting a trench gate type of gate structure, the thickness of the semiconductor substrate corresponding to the breakdown voltage class is designed to be smaller than in a planar gate type semiconductor device. For example, the thickness of the semiconductor substrate after completion in a 600V breakdown voltage class trench gate type IGBT is in the region of 60 μm in the smallest case. There is a tendency for heavy use to be made of trench gate type gate structures, with an object of more effectively producing semiconductor devices. In this way, the thickness of the semiconductor substrate easily falls below 100 μm.
Also, recently, an increase in the diameter of a semiconductor substrate made from silicon from, for example, a diameter of six inches to a diameter of eight inches is being pursued, and an improvement in semiconductor device productivity is being sought. However, when a semiconductor substrate with a diameter of eight inches is reduced to a thickness of in the region of 60 μm in the manufacturing step of a power semiconductor device such as an IGBT, the warpage of the semiconductor substrate increases markedly. Because of this, with the kinds of technology shown in the heretofore described patent documents, it is difficult to chuck or convey a thinner semiconductor substrate or markedly warped semiconductor substrate in a condition in which the flatness of the semiconductor substrate is maintained or increased.
For example, in U.S. Pat. No. 3,627,338 (FIG. 1), U.S. Pat. No. 3,747,282 (FIG. 1), and Japanese Patent No. 2,821,678 (refer to FIG. 20), foreign objects such as dirt or dust become trapped between the semiconductor substrate 1 and a portion 105, other than the groove portions 102, of the base portion 101. When the semiconductor substrate 1 is made thinner as heretofore described, a portion of the semiconductor substrate 1 in contact with a foreign object easily becomes distorted. Also, with the technology shown in JP-B-60-15147 (refer to FIGS. 21 and 22) too, as the portion of the semiconductor substrate 1 not in contact with the protruding portions 112 and peripheral portion 113 sags convexly on the base portion 111 side owing to the suction force when the semiconductor substrate 1 is vacuum drawn, the semiconductor substrate 1 is considerably distorted, and the flatness decreases. As a result of this, for example, exposure resolution in an exposure step decreases markedly.
Also, as disclosed in the technology shown in Japanese Patent No. 4,298,078, when adsorbing a currently mainstream 200 mm (eight inch) diameter semiconductor substrate with a pin chuck type chucking device having protruding portions arrayed in a lattice form, with the interval between adjacent protruding portions at 2 mm, a wafer distortion of approximately 1/2.6 times the flatness of the semiconductor substrate occurs. In the case of the currently mass produced 0.25 μm rule semiconductor process, while the semiconductor substrate flatness tolerance value, taken as ten percent of the 800 nm focal depth, is 80 nm, the tolerance value of the wafer distortion, taken as ten percent of the 50 nm overlay accuracy, is 5 nm. In order to keep the wafer distortion within 5 nm, it is necessary that the semiconductor substrate flatness tolerance value is 13 (=5×2.6) nm, which is far smaller than the 80 nm tolerance value. That is, the semiconductor substrate flatness required for overlay accuracy is far stricter than the semiconductor substrate flatness required for focal depth.
With the technology shown in Japanese Patent No. 4,298,078, when the thickness of the semiconductor substrate is 0.1 mm, it is necessary that the relationship between the chucking force P adsorbing the semiconductor substrate and the interval L between adjacent protruding portions satisfies Equation 3 and Equation 4 below in order to reduce the wafer distortion. To this end, it is necessary that the interval L between adjacent protruding portions is 1.72 mm or less, and that the chucking force holding the semiconductor substrate is 12.4 kN/m2 or less.P≦0.000063/L3  (3)L≦0.00172  (4)
However, as heretofore described, the IGBT power semiconductor device warpage is large, for example, in the case of an eight inch diameter semiconductor substrate, it is not unusual that the semiconductor substrate warpage exceeds 1 mm. Because of this, in order to eliminate the warpage occurring in the semiconductor substrate, and to chuck and hold the semiconductor substrate in a sufficiently stable condition, it is normally necessary that the chucking force holding the semiconductor substrate is in the region of 40 kN/m2 when the thickness of the semiconductor substrate is in the region of 100 μm, which considerably exceeds the 12.4 kN/m2 chucking force holding the semiconductor substrate that satisfies Equation 3 and Equation 4. Because of this, as shown in Japanese Patent No. 4,298,078, one portion of the semiconductor substrate supported with adjacent protruding portions as support points is considerably distorted, and the sagging and wafer distortion of the semiconductor device exceed the tolerance values required in the element design.
Also, with the technology shown in Japanese Patent No. 2,574,818, when the thickness of the semiconductor substrate is 100 μm, and the tolerance range of the sagging of the semiconductor substrate between protruding portions is the heretofore described −0.5 μm or more, +0.5 μm or less, the interval between adjacent protruding portions is approximately 0.7 mm or less. When the interval between adjacent protruding portions is approximately 0.7 mm or less when forming quadrangular pyramidic protruding portions on the base portion using an anisotropic etching, the width of an opening portion of a mask covering a region of the base portion that is not etched is too small, and it is difficult to control the amount removed by etching in the crystal plane orientation. Because of this, controllability of the heights of the protruding portions and the interval between adjacent protruding portions is lost.